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| Microcontrollers ApNote AP2423 : Additional file AP242301.EXE available New ASC Serial Interface Async. Baudrate Calculation with the Fractional Divider The new ASC Asynchronous/Synchronous Serial Interface allows programming of the desired baudrate very precisely in asynchronous modes, depending on the CPU clock rate. This ApNote describes the programming of the baudrate generator (fractional divider and baudrate reload timer) and provides an utility program for optimization of this step. Author : Richard Schmid / HL DC PD MC / Siemens AG Semiconductor Group 07.98, Rel 01 New ASC Serial Interface Async. Baudrate Calculation with the Fractional Divider Contents 1 1.1 1.2 2 2.1 2.2 3 Page Baudrates in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Using the fixed Input Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Using the Fractional Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Comparision between Fractional Divider and Fixed Dividers . . . . . . . . . . . . . . . . . . 5 Improved Baudrate Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Improved Baudrate Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Baudrate Calculation Program ASC.EXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AP2423 ApNote - Revision History Actual Revision : 07.98 Page of Page of actual Rev. prev.Rel. Previous Revision : none (Original Version) Subjects (changes since last release) Semiconductor Group 2 of 6 AP2423 07.98 New ASC Serial Interface Async. Baudrate Calculation with the Fractional Divider 1 Baudrates in Asynchronous Mode The baudrate generator of the new ASC serial interface has an improved baudrate generation circuitry as shown in Figure 1. Generally, the clock divider circuitry, which generates the input clock for the 13-bit baudrate timer, is extended by a fractional divider, which allows now the adjustment of more accurate baudrates and the extension of the baudrate range. SFDE Fractional Divider SFDV fMOD /2 SR /3 Mux fDIV 13-Bit Reload Register SBG fBR Baud Rate Clock Sample Clock /16 13-Bit Baudrate Timer fBRT SFDE SBRS 0 0 1 SBRS 0 1 X Selected Divider /2 /3 Fractional Divider Figure 1 : ASC Baudrate Generator Circuitry in Asynchronous Modes The frequency of the output clock of the baudrate generator depends on the following clock rates, bits, and register values : - - - - frequency of the input clock fMOD selection of the baudrate timer input clock fDIV by bits SFDE and SBRS (in SFR SCON) 9-bit value of register SFDV (if bit SFDE=1 - fractional divider enabled) value of the 13-bit reload register SBG In the asynchronous modes of the ASC the output clock of the baudrate timer with its reload register is the sample clock fBRT. For baudrate calculations, the baudrate clock fBR is derived from this sample clock fBRT by a division by 16. Note: Abbreviations of bits and registers used in this ApNote SBG : ASC Baud Rate Timer/Reload Register SFDV: : ASC Fractional Divider Register SCON : ASC Control Register SFDE : bit SCON.11 SBRS : bit SCON.13 Semiconductor Group 3 of 6 AP2423 07.98 New ASC Serial Interface Async. Baudrate Calculation with the Fractional Divider 1.1 Using the fixed Input Clock Divider The two fixed input clock dividers are still available for compatibility reason with the previous ASC serial interface. The baudrate for asynchronous operation of serial channel ASC when using the fixed input clock divider ratios (SFDE=0) and the required reload value for a given baudrate can be determined by the following formulas : Table 1 : Asynchronous Baudrate Formulas using the Fixed Input Clock Dividers SFDE 0 SBRS 0 SBG 0 ... 8191 Baudrate = SBG = 1 Baudrate = SBG = Formula fMOD 32 x (SBG+1) fMOD 32 x Baudrate fMOD 48 x (SBG+1) fMOD 48 x Baudrate -1 -1 SBG represents the content of the reload register SBG, taken as unsigned 13-bit integer. 1.2 Using the Fractional Divider When the fractional divider is selected, the input clock fDIV for the baudrate timer is derived from the module clock fMOD by a programmable divider. If SFDE=1, the fractional divider is activated, It divides fMOD by a fraction of n/512 for any value of n from 0 to 511. With n=0 (SBG=0), the divider ratio is 1 which means that fDIV = fMOD. Table 2 : Asynchronous Baudrate Formulas using the Fractional Input Clock Divider SFDE 1 SBRS SBG 0 ... 8191 SFDV 1 ... 511 Baudrate = 0 Baudrate = Formula SFDV 512 x fMOD 16 x (SBG+1) fMOD 16 x (SBG+1) SBG represents the content of the reload register SBG, taken as unsigned 13-bit integer. SFDV represents the content of the fractional divider register taken as unsigned 9-bit integer. Semiconductor Group 4 of 6 AP2423 07.98 New ASC Serial Interface Async. Baudrate Calculation with the Fractional Divider 2 2.1 Comparision between Fractional Divider and Fixed Dividers Improved Baudrate Range The baudrate ranges that can be achieved for the asynchronous modes when using the two fixed clock dividers (2 or 3) and a module clock fMOD of 25 MHz is : - 781.25 kBaud down to 63.6 Baud (maximum value = fMOD / 32; minimum value = fMOD / 393216) With the fractional divider and a module clock fMOD of 25 MHz the available baudrate range is : - 1.5625 MBaud down to 0.373 Baud (maximum value = fMOD / 16; minimum value = fMOD / 67108864) This example shows the improved range of the new ASC serial interface in asynchronous mode when using the new fractional divider. 2.2 Improved Baudrate Accuracy The accuracy of a requested baudrate derived from a fixed module clock fMOD is also a feature which has been improved with the fractional divider. Example : requested baudrate = 19.2 kBaud at fMOD = 25 MHz With the two fixed clock dividers (2 or 3) the accuracy is : - - 0.76% (with 2 prescaler selected and SBG = 40) - + 0.45% (with 3 prescaler selected and SBG = 26) With the fractional divider the following accuracy can be achieved : - 0.01% (see the example in chapter 3) This example shows the drastically improved accuracy of the adjustment for baudrates of the new ASC serial interface in asynchronous mode when using the new fractional divider. For optimization of the fractional divider parameters (SFDV and SBG have to be calculated), an utility program has been created which allows to select the best SFDV/SBG parameter cobination for a specific accuracy. Semiconductor Group 5 of 6 AP2423 07.98 New ASC Serial Interface Async. Baudrate Calculation with the Fractional Divider 3 Baudrate Calculation Program ASC.EXE The program ASC.EXE calculates the two divide factors needed for the new ASC module when using the fractional divider for baudrate calculation. The other baudrate generator modes (fixed dividers) are not considered, because they are included only for backward compatibility and provide much worse accuracy. The program is able to find any combination of the two parameters which satisfies the required baudrate based on the module input clock and the requested accuracy. At the first time the program should be started with the maximum accuracy of 0.01% to limit the size of the output file. Only if there are no valid parameters the accuracy requirements can be reduced step by step. The program file AP242301.EXE (selfextracting ZIP file) contains : - the program ASC.EXE - an example of the generated output file ASC.TXT - a readme file README.TXT It has to be noted, that the program currently makes no consistancy checks (like to ensure that the baudrate is less than fMOD/16 etc.) Note : ASC.EXE runs only on a PC (DOS, WINDOWS) not on SUN (UNIX) workstations ! The example below shows the content of the output file ASC.TXT (generated by ASC.EXE) when the follwing parameters are used : - 25 MHz ASC module clock rate (fMOD) - 19.2 kBaud baudrate requested - accuracy at least 0.01 % Baudrate calculation program (V0.1) for the ASC module when using the fractional divider (SFDE=1) ================================================= Selected module clock rate : 25000000 Hz Requested baudrate : 19200 Baud Selected max. deviation : 0.01 % ================================================= SFDV SBG Baudrate Deviation abs. rel. ------------------------------------------------151 23 19201 1 0.0000 302 47 19201 1 0.0000 346 54 19198 -2 -0.0001 453 71 19201 1 0.0000 497 78 19199 -1 -0.0001 ------------------------------------------------5 combinations found With this example, four combinations of SFDV and SBG values have been found with a minimum error of < 1 Baud within the limit of 0.01%. These combinations can be then used for baudrate programming. Semiconductor Group 6 of 6 AP2423 07.98 |
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